H5M1G22MFR-J3M 較新到貨

時間：2014-02-20作者：深圳深益科技發(fā)展有限公司瀏覽：133

H5MS1G22MFR-J3M 深益科技發(fā)展有限公司全新****銷售

FEATURES SUMMARY
● Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
● Mobile DDR SDRAM INTERFACE
- x32 bus width
- Multiplexed Address (Row address and Column ad-
dress)
● SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
● MEMORY CELL ARRAY
- 1Gbit (x32 device) = 8M x 4Bank x 32 I/O
● DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
● LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
● INPUT CLOCK
- Differential clock inputs (CK, CK)
● Data MASK
- DM0 ~ DM3: Input mask **s for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
● MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
● CAS LATENCY
- Programmable CAS latency 2 or 3 supported
● BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
● AUTO PRECHARGE
- Option for each burst access
● AUTO REFRESH AND SELF REFRESH MODE
● CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
● INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
● Operation Temperature
- -30
oC ~ 85oC
● PACKAGE
- 90 Ball Lead Free FBGA
● ADDRESS TABLE
Note)Reduced Page size:16,384 rows by 512 columns by 32

 


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